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-rw-r--r--stm32.h69
1 files changed, 69 insertions, 0 deletions
diff --git a/stm32.h b/stm32.h
index 891ba78..da84bfc 100644
--- a/stm32.h
+++ b/stm32.h
@@ -14,6 +14,75 @@ struct RCC_t {
volatile uint32_t APB1ENR;
volatile uint32_t BDCR;
volatile uint32_t CSR;
+
+ enum AHB_dev {
+ DMA1 = 1 << 0,
+ DMA2 = 1 << 1,
+ SRAM = 1 << 2,
+ FLITF = 1 << 4,
+ CRC = 1 << 6,
+ FSMC = 1 << 8,
+ SDIO = 1 << 10
+ };
+
+ enum APB1_dev {
+ TIM2 = 1 << 0,
+ TIM3 = 1 << 1,
+ TIM4 = 1 << 2,
+ TIM5 = 1 << 3,
+ TIM6 = 1 << 4,
+ TIM7 = 1 << 5,
+ TIM12 = 1 << 6,
+ TIM13 = 1 << 7,
+ TIM14 = 1 << 8,
+ WWDG = 1 << 11,
+ SPI2 = 1 << 14,
+ SPI3 = 1 << 15,
+ USART2 = 1 << 17,
+ USART3 = 1 << 18,
+ UART4 = 1 << 19,
+ UART5 = 1 << 20,
+ I2C1 = 1 << 21,
+ I2C2 = 1 << 22,
+ USB = 1 << 23,
+ CAN = 1 << 25,
+ BKP = 1 << 27,
+ PWR = 1 << 28,
+ DAC = 1 << 29
+ };
+
+ enum APB2_dev {
+ AFIO = 1 << 0,
+ IOPA = 1 << 2,
+ IOPB = 1 << 3,
+ IOPC = 1 << 4,
+ IOPD = 1 << 5,
+ IOPE = 1 << 6,
+ IOPF = 1 << 7,
+ IOPG = 1 << 8,
+ ADC1 = 1 << 9,
+ ADC2 = 1 << 10,
+ TIM1 = 1 << 11,
+ SPI1 = 1 << 12,
+ TIM8 = 1 << 13,
+ USART1 = 1 << 14,
+ ADC3 = 1 << 15,
+ TIM9 = 1 << 19,
+ TIM10 = 1 << 20,
+ TIM11 = 1 << 21
+ };
+
+ inline void enable(AHB_dev dev) {
+ AHBENR |= dev;
+ }
+
+ inline void enable(APB1_dev dev) {
+ APB1ENR |= dev;
+ }
+
+ inline void enable(APB2_dev dev) {
+ APB2ENR |= dev;
+ }
};
static RCC_t& RCC = *(RCC_t*)0x40021000;