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#ifndef STM32_H
#define STM32_H
#include <stdint.h>
struct NVIC_t {
volatile uint32_t ISER[32];
volatile uint32_t ICER[32];
volatile uint32_t ISPR[32];
volatile uint32_t ICPR[32];
volatile uint32_t IABR[64];
volatile uint8_t IPR[2816];
volatile uint32_t STIR;
};
static NVIC_t& NVIC = *(NVIC_t*)0xe000e100;
struct SCB_t {
volatile uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint8_t SHPR[12];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMAR;
volatile uint32_t BFAR;
};
static SCB_t& SCB = *(SCB_t*)0xe000ed00;
struct RCC_t {
#if defined(STM32F1)
volatile uint32_t CR;
volatile uint32_t CFGR;
volatile uint32_t CIR;
volatile uint32_t APB2RSTR;
volatile uint32_t APB1RSTR;
volatile uint32_t AHBENR;
volatile uint32_t APB2ENR;
volatile uint32_t APB1ENR;
volatile uint32_t BDCR;
volatile uint32_t CSR;
#elif defined(STM32F4)
volatile uint32_t CR;
volatile uint32_t PLLCFGR;
volatile uint32_t CFGR;
volatile uint32_t CIR;
volatile uint32_t AHB1RSTR;
volatile uint32_t AHB2RSTR;
volatile uint32_t AHB3RSTR;
volatile uint32_t AHB4RSTR; // Reserved
volatile uint32_t APB1RSTR;
volatile uint32_t APB2RSTR;
volatile uint32_t APB3RSTR; // Reserved
volatile uint32_t APB4RSTR; // Reserved
volatile uint32_t AHB1ENR;
volatile uint32_t AHB2ENR;
volatile uint32_t AHB3ENR;
volatile uint32_t AHB4ENR; // Reserved
volatile uint32_t APB1ENR;
volatile uint32_t APB2ENR;
volatile uint32_t APB3ENR; // Reserved
volatile uint32_t APB4ENR; // Reserved
volatile uint32_t AHB1LPENR;
volatile uint32_t AHB2LPENR;
volatile uint32_t AHB3LPENR;
volatile uint32_t AHB4LPENR; // Reserved
volatile uint32_t APB1LPENR;
volatile uint32_t APB2LPENR;
volatile uint32_t APB3LPENR; // Reserved
volatile uint32_t APB4LPENR; // Reserved
volatile uint32_t BDCR;
volatile uint32_t CSR;
volatile uint32_t _1;
volatile uint32_t _2;
volatile uint32_t SSCGR;
volatile uint32_t PLLI2SCFGR;
#endif
#if defined(STM32F1)
enum AHB_dev {
DMA1 = 1 << 0,
DMA2 = 1 << 1,
SRAM = 1 << 2,
FLITF = 1 << 4,
CRC = 1 << 6,
FSMC = 1 << 8,
SDIO = 1 << 10
};
enum APB1_dev {
TIM2 = 1 << 0,
TIM3 = 1 << 1,
TIM4 = 1 << 2,
TIM5 = 1 << 3,
TIM6 = 1 << 4,
TIM7 = 1 << 5,
TIM12 = 1 << 6,
TIM13 = 1 << 7,
TIM14 = 1 << 8,
WWDG = 1 << 11,
SPI2 = 1 << 14,
SPI3 = 1 << 15,
USART2 = 1 << 17,
USART3 = 1 << 18,
UART4 = 1 << 19,
UART5 = 1 << 20,
I2C1 = 1 << 21,
I2C2 = 1 << 22,
USB = 1 << 23,
CAN = 1 << 25,
BKP = 1 << 27,
PWR = 1 << 28,
DAC = 1 << 29
};
enum APB2_dev {
AFIO = 1 << 0,
IOPA = 1 << 2,
IOPB = 1 << 3,
IOPC = 1 << 4,
IOPD = 1 << 5,
IOPE = 1 << 6,
IOPF = 1 << 7,
IOPG = 1 << 8,
ADC1 = 1 << 9,
ADC2 = 1 << 10,
TIM1 = 1 << 11,
SPI1 = 1 << 12,
TIM8 = 1 << 13,
USART1 = 1 << 14,
ADC3 = 1 << 15,
TIM9 = 1 << 19,
TIM10 = 1 << 20,
TIM11 = 1 << 21
};
#elif defined(STM32F4)
enum AHB1_dev {
GPIOA = 1 << 0,
GPIOB = 1 << 1,
GPIOC = 1 << 2,
GPIOD = 1 << 3,
GPIOE = 1 << 4,
GPIOF = 1 << 5,
GPIOG = 1 << 6,
GPIOH = 1 << 7,
GPIOI = 1 << 8,
CRC = 1 << 12,
DMA1 = 1 << 21,
DMA2 = 1 << 22,
ETHMAC = 1 << 25,
OTGHS = 1 << 29,
};
enum AHB2_dev {
DCMI = 1 << 0,
CRYP = 1 << 4,
HASH = 1 << 5,
RNG = 1 << 6,
OTGFS = 1 << 7,
};
enum AHB3_dev {
FSMC = 1 << 0,
};
enum APB1_dev {
TIM2 = 1 << 0,
TIM3 = 1 << 1,
TIM4 = 1 << 2,
TIM5 = 1 << 3,
TIM6 = 1 << 4,
TIM7 = 1 << 5,
TIM12 = 1 << 6,
TIM13 = 1 << 7,
TIM14 = 1 << 8,
WWDG = 1 << 11,
SPI2 = 1 << 14,
SPI3 = 1 << 15,
USART2 = 1 << 17,
USART3 = 1 << 18,
UART4 = 1 << 19,
UART5 = 1 << 20,
I2C1 = 1 << 21,
I2C2 = 1 << 22,
I2C3 = 1 << 23,
CAN1 = 1 << 25,
CAN2 = 1 << 26,
PWR = 1 << 28,
DAC = 1 << 29,
};
enum APB2_dev {
TIM1 = 1 << 0,
TIM8 = 1 << 1,
USART1 = 1 << 4,
USART6 = 1 << 5,
ADC = 1 << 8,
SDIO = 1 << 11,
SPI1 = 1 << 12,
SYSCFG = 1 << 14,
TIM9 = 1 << 16,
TIM10 = 1 << 17,
TIM11 = 1 << 18,
};
#endif
#if defined(STM32F1)
inline void enable(AHB_dev dev) {
AHBENR |= dev;
}
#elif defined(STM32F4)
inline void enable(AHB1_dev dev) {
AHB1ENR |= dev;
}
inline void enable(AHB2_dev dev) {
AHB2ENR |= dev;
}
inline void enable(AHB3_dev dev) {
AHB3ENR |= dev;
}
#endif
inline void enable(APB1_dev dev) {
APB1ENR |= dev;
}
inline void enable(APB2_dev dev) {
APB2ENR |= dev;
}
};
#if defined(STM32F1)
static RCC_t& RCC = *(RCC_t*)0x40021000;
#elif defined(STM32F4)
static RCC_t& RCC = *(RCC_t*)0x40023800;
#endif
struct STK_t {
volatile uint32_t CTRL;
volatile uint32_t LOAD;
volatile uint32_t VAL;
volatile uint32_t CALIB;
};
static STK_t& STK = *(STK_t*)0xe000e010;
struct FLASH_t {
volatile uint32_t ACR;
volatile uint32_t KEYR;
volatile uint32_t OPTKEYR;
volatile uint32_t SR;
volatile uint32_t CR;
#if defined(STM32F1)
volatile uint32_t AR;
volatile uint32_t RESERVED;
volatile uint32_t OBR;
volatile uint32_t WRPR;
#elif defined(STM32F4)
volatile uint32_t OPTCR;
#endif
};
#if defined(STM32F1)
static FLASH_t& FLASH = *(FLASH_t*)0x40022000;
#elif defined(STM32F4)
static FLASH_t& FLASH = *(FLASH_t*)0x40023c00;
#endif
struct I2C_t {
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t OAR1;
volatile uint32_t OAR2;
volatile uint32_t DR;
volatile uint32_t SR1;
volatile uint32_t SR2;
volatile uint32_t CCR;
volatile uint32_t TRISE;
};
static I2C_t& I2C1 = *(I2C_t*)0x40005400;
static I2C_t& I2C2 = *(I2C_t*)0x40005800;
struct USART_t {
volatile uint32_t SR;
volatile uint32_t DR;
volatile uint32_t BRR;
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t CR3;
volatile uint32_t GTPR;
};
#if defined(STM32F1)
static USART_t& USART1 = *(USART_t*)0x40013800;
static USART_t& USART2 = *(USART_t*)0x40004400;
static USART_t& USART3 = *(USART_t*)0x40004800;
#elif defined(STM32F4)
static USART_t& USART1 = *(USART_t*)0x40011000;
static USART_t& USART2 = *(USART_t*)0x40004400;
static USART_t& USART3 = *(USART_t*)0x40004800;
#endif
struct TIM_t {
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t SMCR;
volatile uint32_t DIER;
volatile uint32_t SR;
volatile uint32_t EGR;
volatile uint32_t CCMR1;
volatile uint32_t CCMR2;
volatile uint32_t CCER;
volatile uint32_t CNT;
volatile uint32_t PSC;
volatile uint32_t ARR;
volatile uint32_t RCR;
volatile uint32_t CCR1;
volatile uint32_t CCR2;
volatile uint32_t CCR3;
volatile uint32_t CCR4;
volatile uint32_t BDTR;
volatile uint32_t DCR;
volatile uint32_t DMAR;
};
static TIM_t& TIM1 = *(TIM_t*)0x40012c00;
static TIM_t& TIM2 = *(TIM_t*)0x40000000;
static TIM_t& TIM3 = *(TIM_t*)0x40000400;
static TIM_t& TIM4 = *(TIM_t*)0x40000800;
static TIM_t& TIM5 = *(TIM_t*)0x40000c00;
static TIM_t& TIM6 = *(TIM_t*)0x40001000;
static TIM_t& TIM7 = *(TIM_t*)0x40001400;
static TIM_t& TIM8 = *(TIM_t*)0x40013400;
struct ADC_t {
volatile uint32_t SR;
volatile uint32_t CR1;
volatile uint32_t CR2;
volatile uint32_t SMPR1;
volatile uint32_t SMPR2;
volatile uint32_t JOFR1;
volatile uint32_t JOFR2;
volatile uint32_t JOFR3;
volatile uint32_t JOFR4;
volatile uint32_t HTR;
volatile uint32_t LTR;
volatile uint32_t SQR1;
volatile uint32_t SQR2;
volatile uint32_t SQR3;
volatile uint32_t JSQR;
volatile uint32_t JDR1;
volatile uint32_t JDR2;
volatile uint32_t JDR3;
volatile uint32_t JDR4;
volatile uint32_t DR;
};
static ADC_t& ADC1 = *(ADC_t*)0x40012400;
static ADC_t& ADC2 = *(ADC_t*)0x40012800;
static ADC_t& ADC3 = *(ADC_t*)0x40013c00;
struct DMA_t {
struct CH_t {
volatile uint32_t CCR;
volatile uint32_t CNDTR;
volatile uint32_t CPAR;
volatile uint32_t CMAR;
uint32_t _reserved;
};
volatile uint32_t ISR;
volatile uint32_t IFCR;
CH_t CH[7];
};
static DMA_t& DMA1 = *(DMA_t*)0x40020000;
static DMA_t& DMA2 = *(DMA_t*)0x40020400;
#endif
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