summaryrefslogtreecommitdiff
path: root/stm32.h
blob: 8144e80c32aec6af886087b4357cdc9cbfdbe788 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
#ifndef STM32_H
#define STM32_H

#include <stdint.h>

struct NVIC_t {
	volatile uint32_t ISER[32];
	volatile uint32_t ICER[32];
	volatile uint32_t ISPR[32];
	volatile uint32_t ICPR[32];
	volatile uint32_t IABR[64];
	volatile uint8_t IPR[2816];
	volatile uint32_t STIR;
};

static NVIC_t& NVIC = *(NVIC_t*)0xe000e100;

struct SCB_t {
	volatile uint32_t CPUID;
	volatile uint32_t ICSR;
	volatile uint32_t VTOR;
	volatile uint32_t AIRCR;
	volatile uint32_t SCR;
	volatile uint32_t CCR;
	volatile uint8_t SHPR[12];
	volatile uint32_t SHCSR;
	volatile uint32_t CFSR;
	volatile uint32_t HFSR;
	volatile uint32_t DFSR;
	volatile uint32_t MMAR;
	volatile uint32_t BFAR;
};

static SCB_t& SCB = *(SCB_t*)0xe000ed00;

struct RCC_t {
	volatile uint32_t CR;
	volatile uint32_t CFGR;
	volatile uint32_t CIR;
	volatile uint32_t APB2RSTR;
	volatile uint32_t APB1RSTR;
	volatile uint32_t AHBENR;
	volatile uint32_t APB2ENR;
	volatile uint32_t APB1ENR;
	volatile uint32_t BDCR;
	volatile uint32_t CSR;
	
	enum AHB_dev {
		DMA1  = 1 << 0,
		DMA2  = 1 << 1,
		SRAM  = 1 << 2,
		FLITF = 1 << 4,
		CRC   = 1 << 6,
		FSMC  = 1 << 8,
		SDIO  = 1 << 10
	};
	
	enum APB1_dev {
		TIM2   = 1 << 0,
		TIM3   = 1 << 1,
		TIM4   = 1 << 2,
		TIM5   = 1 << 3,
		TIM6   = 1 << 4,
		TIM7   = 1 << 5,
		TIM12  = 1 << 6,
		TIM13  = 1 << 7,
		TIM14  = 1 << 8,
		WWDG   = 1 << 11,
		SPI2   = 1 << 14,
		SPI3   = 1 << 15,
		USART2 = 1 << 17,
		USART3 = 1 << 18,
		UART4  = 1 << 19,
		UART5  = 1 << 20,
		I2C1   = 1 << 21,
		I2C2   = 1 << 22,
		USB    = 1 << 23,
		CAN    = 1 << 25,
		BKP    = 1 << 27,
		PWR    = 1 << 28,
		DAC    = 1 << 29
	};
	
	enum APB2_dev {
		AFIO   = 1 << 0,
		IOPA   = 1 << 2,
		IOPB   = 1 << 3,
		IOPC   = 1 << 4,
		IOPD   = 1 << 5,
		IOPE   = 1 << 6,
		IOPF   = 1 << 7,
		IOPG   = 1 << 8,
		ADC1   = 1 << 9,
		ADC2   = 1 << 10,
		TIM1   = 1 << 11,
		SPI1   = 1 << 12,
		TIM8   = 1 << 13,
		USART1 = 1 << 14,
		ADC3   = 1 << 15,
		TIM9   = 1 << 19,
		TIM10  = 1 << 20,
		TIM11  = 1 << 21
	};
	
	inline void enable(AHB_dev dev) {
		AHBENR |= dev;
	}
	
	inline void enable(APB1_dev dev) {
		APB1ENR |= dev;
	}
	
	inline void enable(APB2_dev dev) {
		APB2ENR |= dev;
	}
};

static RCC_t& RCC = *(RCC_t*)0x40021000;

struct STK_t {
	volatile uint32_t CTRL;
	volatile uint32_t LOAD;
	volatile uint32_t VAL;
	volatile uint32_t CALIB;
};

static STK_t& STK = *(STK_t*)0xe000e010;

struct FLASH_t {
	volatile uint32_t ACR;
	volatile uint32_t KEYR;
	volatile uint32_t OPTKEYR;
	volatile uint32_t SR;
	volatile uint32_t CR;
	volatile uint32_t AR;
	volatile uint32_t RESERVED;
	volatile uint32_t OBR;
	volatile uint32_t WRPR;
};

static FLASH_t& FLASH = *(FLASH_t*)0x40022000;

struct GPIO_t {
	volatile uint32_t CRL;
	volatile uint32_t CRH;
	volatile uint32_t IDR;
	volatile uint32_t ODR;
	volatile uint32_t BSRR;
	volatile uint32_t BRR;
	volatile uint32_t LCKR;
};

static GPIO_t& GPIOA = *(GPIO_t*)0x40010800;
static GPIO_t& GPIOB = *(GPIO_t*)0x40010c00;
static GPIO_t& GPIOC = *(GPIO_t*)0x40011000;

struct I2C_t {
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t OAR1;
	volatile uint32_t OAR2;
	volatile uint32_t DR;
	volatile uint32_t SR1;
	volatile uint32_t SR2;
	volatile uint32_t CCR;
	volatile uint32_t TRISE;
};

static I2C_t& I2C1 = *(I2C_t*)0x40005400;
static I2C_t& I2C2 = *(I2C_t*)0x40005800;

struct USART_t {
	volatile uint32_t SR;
	volatile uint32_t DR;
	volatile uint32_t BRR;
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t CR3;
	volatile uint32_t GTPR;
};

static USART_t& USART1 = *(USART_t*)0x40013800;
static USART_t& USART2 = *(USART_t*)0x40004400;
static USART_t& USART3 = *(USART_t*)0x40004800;

struct TIM_t {
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t SMCR;
	volatile uint32_t DIER;
	volatile uint32_t SR;
	volatile uint32_t EGR;
	volatile uint32_t CCMR1;
	volatile uint32_t CCMR2;
	volatile uint32_t CCER;
	volatile uint32_t CNT;
	volatile uint32_t PSC;
	volatile uint32_t ARR;
	volatile uint32_t RCR;
	volatile uint32_t CCR1;
	volatile uint32_t CCR2;
	volatile uint32_t CCR3;
	volatile uint32_t CCR4;
	volatile uint32_t BDTR;
	volatile uint32_t DCR;
	volatile uint32_t DMAR;
};

static TIM_t& TIM1 = *(TIM_t*)0x40012c00;
static TIM_t& TIM2 = *(TIM_t*)0x40000000;
static TIM_t& TIM3 = *(TIM_t*)0x40000400;
static TIM_t& TIM4 = *(TIM_t*)0x40000800;
static TIM_t& TIM5 = *(TIM_t*)0x40000c00;
static TIM_t& TIM6 = *(TIM_t*)0x40001000;
static TIM_t& TIM7 = *(TIM_t*)0x40001400;
static TIM_t& TIM8 = *(TIM_t*)0x40013400;

struct ADC_t {
	volatile uint32_t SR;
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t SMPR1;
	volatile uint32_t SMPR2;
	volatile uint32_t JOFR1;
	volatile uint32_t JOFR2;
	volatile uint32_t JOFR3;
	volatile uint32_t JOFR4;
	volatile uint32_t HTR;
	volatile uint32_t LTR;
	volatile uint32_t SQR1;
	volatile uint32_t SQR2;
	volatile uint32_t SQR3;
	volatile uint32_t JSQR;
	volatile uint32_t JDR1;
	volatile uint32_t JDR2;
	volatile uint32_t JDR3;
	volatile uint32_t JDR4;
	volatile uint32_t DR;
};

static ADC_t& ADC1 = *(ADC_t*)0x40012400;
static ADC_t& ADC2 = *(ADC_t*)0x40012800;
static ADC_t& ADC3 = *(ADC_t*)0x40013c00;

struct DMA_t {
	struct CH_t {
		volatile uint32_t CCR;
		volatile uint32_t CNDTR;
		volatile uint32_t CPAR;
		volatile uint32_t CMAR;
		uint32_t _reserved;
	};
	
	volatile uint32_t ISR;
	volatile uint32_t IFCR;
	CH_t CH[7];
};

static DMA_t& DMA1 = *(DMA_t*)0x40020000;
static DMA_t& DMA2 = *(DMA_t*)0x40020400;

#endif