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-rw-r--r--drivers/gps.h1
-rw-r--r--drivers/ppmsum.cpp2
-rw-r--r--hal/flash.cpp17
-rw-r--r--hal/flash.h30
-rw-r--r--hal/i2c.cpp1
-rw-r--r--hal/rcc.cpp13
-rw-r--r--hal/rcc.h211
-rw-r--r--hal/stm32.h231
-rw-r--r--hal/usart.h1
9 files changed, 267 insertions, 240 deletions
diff --git a/drivers/gps.h b/drivers/gps.h
index c37fc8a..786b719 100644
--- a/drivers/gps.h
+++ b/drivers/gps.h
@@ -1,6 +1,7 @@
#ifndef GPS_H
#define GPS_H
+#include "rcc.h"
#include "stm32.h"
#include "interrupt.h"
#include "thread.h"
diff --git a/drivers/ppmsum.cpp b/drivers/ppmsum.cpp
index 2beaccb..ff00f42 100644
--- a/drivers/ppmsum.cpp
+++ b/drivers/ppmsum.cpp
@@ -1,5 +1,7 @@
#include "ppmsum.h"
+#include "rcc.h"
+
PPMSum* PPMSum::self = 0;
template<>
diff --git a/hal/flash.cpp b/hal/flash.cpp
new file mode 100644
index 0000000..2b0fb69
--- /dev/null
+++ b/hal/flash.cpp
@@ -0,0 +1,17 @@
+#include "flash.h"
+
+void flash_init() {
+ #if defined(STM32F1)
+
+ // Set flash latency.
+ FLASH.ACR = 0x12;
+
+ #elif defined(STM32F4)
+
+ // Set flash latency.
+ FLASH.ACR = 0x105;
+
+ while(FLASH.ACR != 0x105);
+
+ #endif
+}
diff --git a/hal/flash.h b/hal/flash.h
new file mode 100644
index 0000000..30d30a5
--- /dev/null
+++ b/hal/flash.h
@@ -0,0 +1,30 @@
+#ifndef FLASH_H
+#define FLASH_H
+
+#include <stdint.h>
+
+struct FLASH_t {
+ volatile uint32_t ACR;
+ volatile uint32_t KEYR;
+ volatile uint32_t OPTKEYR;
+ volatile uint32_t SR;
+ volatile uint32_t CR;
+ #if defined(STM32F1)
+ volatile uint32_t AR;
+ volatile uint32_t RESERVED;
+ volatile uint32_t OBR;
+ volatile uint32_t WRPR;
+ #elif defined(STM32F4)
+ volatile uint32_t OPTCR;
+ #endif
+};
+
+#if defined(STM32F1)
+static FLASH_t& FLASH = *(FLASH_t*)0x40022000;
+#elif defined(STM32F4)
+static FLASH_t& FLASH = *(FLASH_t*)0x40023c00;
+#endif
+
+void flash_init();
+
+#endif
diff --git a/hal/i2c.cpp b/hal/i2c.cpp
index cee72ec..867597a 100644
--- a/hal/i2c.cpp
+++ b/hal/i2c.cpp
@@ -1,5 +1,6 @@
#include "i2c.h"
+#include "rcc.h"
#include "stm32.h"
#include "thread.h"
diff --git a/hal/rcc.cpp b/hal/rcc.cpp
index 5a82d62..57b8f7d 100644
--- a/hal/rcc.cpp
+++ b/hal/rcc.cpp
@@ -1,11 +1,11 @@
#include "rcc.h"
-#include "stm32.h"
+#include "flash.h"
void rcc_init() {
- #if defined(STM32F1)
+ // Initialize flash.
+ flash_init();
- // Set flash latency.
- FLASH.ACR = 0x12;
+ #if defined(STM32F1)
// Enable HSE.
RCC.CR |= 0x10000;
@@ -28,11 +28,6 @@ void rcc_init() {
#elif defined(STM32F4)
- // Set flash latency.
- FLASH.ACR = 0x105;
-
- while(FLASH.ACR != 0x105);
-
// Enable HSE.
RCC.CR |= 0x10000;
while(!(RCC.CR & 0x20000));
diff --git a/hal/rcc.h b/hal/rcc.h
index 8c5fb86..4b8d99f 100644
--- a/hal/rcc.h
+++ b/hal/rcc.h
@@ -1,6 +1,217 @@
#ifndef RCC_H
#define RCC_H
+#include <stdint.h>
+
+struct RCC_t {
+ #if defined(STM32F1)
+ volatile uint32_t CR;
+ volatile uint32_t CFGR;
+ volatile uint32_t CIR;
+ volatile uint32_t APB2RSTR;
+ volatile uint32_t APB1RSTR;
+ volatile uint32_t AHBENR;
+ volatile uint32_t APB2ENR;
+ volatile uint32_t APB1ENR;
+ volatile uint32_t BDCR;
+ volatile uint32_t CSR;
+ #elif defined(STM32F4)
+ volatile uint32_t CR;
+ volatile uint32_t PLLCFGR;
+ volatile uint32_t CFGR;
+ volatile uint32_t CIR;
+ volatile uint32_t AHB1RSTR;
+ volatile uint32_t AHB2RSTR;
+ volatile uint32_t AHB3RSTR;
+ volatile uint32_t AHB4RSTR; // Reserved
+ volatile uint32_t APB1RSTR;
+ volatile uint32_t APB2RSTR;
+ volatile uint32_t APB3RSTR; // Reserved
+ volatile uint32_t APB4RSTR; // Reserved
+ volatile uint32_t AHB1ENR;
+ volatile uint32_t AHB2ENR;
+ volatile uint32_t AHB3ENR;
+ volatile uint32_t AHB4ENR; // Reserved
+ volatile uint32_t APB1ENR;
+ volatile uint32_t APB2ENR;
+ volatile uint32_t APB3ENR; // Reserved
+ volatile uint32_t APB4ENR; // Reserved
+ volatile uint32_t AHB1LPENR;
+ volatile uint32_t AHB2LPENR;
+ volatile uint32_t AHB3LPENR;
+ volatile uint32_t AHB4LPENR; // Reserved
+ volatile uint32_t APB1LPENR;
+ volatile uint32_t APB2LPENR;
+ volatile uint32_t APB3LPENR; // Reserved
+ volatile uint32_t APB4LPENR; // Reserved
+ volatile uint32_t BDCR;
+ volatile uint32_t CSR;
+ volatile uint32_t _1;
+ volatile uint32_t _2;
+ volatile uint32_t SSCGR;
+ volatile uint32_t PLLI2SCFGR;
+ #endif
+
+ #if defined(STM32F1)
+ enum AHB_dev {
+ DMA1 = 1 << 0,
+ DMA2 = 1 << 1,
+ SRAM = 1 << 2,
+ FLITF = 1 << 4,
+ CRC = 1 << 6,
+ FSMC = 1 << 8,
+ SDIO = 1 << 10
+ };
+
+ enum APB1_dev {
+ TIM2 = 1 << 0,
+ TIM3 = 1 << 1,
+ TIM4 = 1 << 2,
+ TIM5 = 1 << 3,
+ TIM6 = 1 << 4,
+ TIM7 = 1 << 5,
+ TIM12 = 1 << 6,
+ TIM13 = 1 << 7,
+ TIM14 = 1 << 8,
+ WWDG = 1 << 11,
+ SPI2 = 1 << 14,
+ SPI3 = 1 << 15,
+ USART2 = 1 << 17,
+ USART3 = 1 << 18,
+ UART4 = 1 << 19,
+ UART5 = 1 << 20,
+ I2C1 = 1 << 21,
+ I2C2 = 1 << 22,
+ USB = 1 << 23,
+ CAN = 1 << 25,
+ BKP = 1 << 27,
+ PWR = 1 << 28,
+ DAC = 1 << 29
+ };
+
+ enum APB2_dev {
+ AFIO = 1 << 0,
+ IOPA = 1 << 2,
+ IOPB = 1 << 3,
+ IOPC = 1 << 4,
+ IOPD = 1 << 5,
+ IOPE = 1 << 6,
+ IOPF = 1 << 7,
+ IOPG = 1 << 8,
+ ADC1 = 1 << 9,
+ ADC2 = 1 << 10,
+ TIM1 = 1 << 11,
+ SPI1 = 1 << 12,
+ TIM8 = 1 << 13,
+ USART1 = 1 << 14,
+ ADC3 = 1 << 15,
+ TIM9 = 1 << 19,
+ TIM10 = 1 << 20,
+ TIM11 = 1 << 21
+ };
+ #elif defined(STM32F4)
+ enum AHB1_dev {
+ GPIOA = 1 << 0,
+ GPIOB = 1 << 1,
+ GPIOC = 1 << 2,
+ GPIOD = 1 << 3,
+ GPIOE = 1 << 4,
+ GPIOF = 1 << 5,
+ GPIOG = 1 << 6,
+ GPIOH = 1 << 7,
+ GPIOI = 1 << 8,
+ CRC = 1 << 12,
+ DMA1 = 1 << 21,
+ DMA2 = 1 << 22,
+ ETHMAC = 1 << 25,
+ OTGHS = 1 << 29,
+ };
+
+ enum AHB2_dev {
+ DCMI = 1 << 0,
+ CRYP = 1 << 4,
+ HASH = 1 << 5,
+ RNG = 1 << 6,
+ OTGFS = 1 << 7,
+ };
+
+ enum AHB3_dev {
+ FSMC = 1 << 0,
+ };
+
+ enum APB1_dev {
+ TIM2 = 1 << 0,
+ TIM3 = 1 << 1,
+ TIM4 = 1 << 2,
+ TIM5 = 1 << 3,
+ TIM6 = 1 << 4,
+ TIM7 = 1 << 5,
+ TIM12 = 1 << 6,
+ TIM13 = 1 << 7,
+ TIM14 = 1 << 8,
+ WWDG = 1 << 11,
+ SPI2 = 1 << 14,
+ SPI3 = 1 << 15,
+ USART2 = 1 << 17,
+ USART3 = 1 << 18,
+ UART4 = 1 << 19,
+ UART5 = 1 << 20,
+ I2C1 = 1 << 21,
+ I2C2 = 1 << 22,
+ I2C3 = 1 << 23,
+ CAN1 = 1 << 25,
+ CAN2 = 1 << 26,
+ PWR = 1 << 28,
+ DAC = 1 << 29,
+ };
+
+ enum APB2_dev {
+ TIM1 = 1 << 0,
+ TIM8 = 1 << 1,
+ USART1 = 1 << 4,
+ USART6 = 1 << 5,
+ ADC = 1 << 8,
+ SDIO = 1 << 11,
+ SPI1 = 1 << 12,
+ SYSCFG = 1 << 14,
+ TIM9 = 1 << 16,
+ TIM10 = 1 << 17,
+ TIM11 = 1 << 18,
+ };
+ #endif
+
+ #if defined(STM32F1)
+ inline void enable(AHB_dev dev) {
+ AHBENR |= dev;
+ }
+ #elif defined(STM32F4)
+ inline void enable(AHB1_dev dev) {
+ AHB1ENR |= dev;
+ }
+
+ inline void enable(AHB2_dev dev) {
+ AHB2ENR |= dev;
+ }
+
+ inline void enable(AHB3_dev dev) {
+ AHB3ENR |= dev;
+ }
+ #endif
+ inline void enable(APB1_dev dev) {
+ APB1ENR |= dev;
+ }
+
+ inline void enable(APB2_dev dev) {
+ APB2ENR |= dev;
+ }
+};
+
+#if defined(STM32F1)
+static RCC_t& RCC = *(RCC_t*)0x40021000;
+#elif defined(STM32F4)
+static RCC_t& RCC = *(RCC_t*)0x40023800;
+#endif
+
void rcc_init();
#endif
diff --git a/hal/stm32.h b/hal/stm32.h
index c487cd4..41ebbb7 100644
--- a/hal/stm32.h
+++ b/hal/stm32.h
@@ -33,215 +33,6 @@ struct SCB_t {
static SCB_t& SCB = *(SCB_t*)0xe000ed00;
-struct RCC_t {
- #if defined(STM32F1)
- volatile uint32_t CR;
- volatile uint32_t CFGR;
- volatile uint32_t CIR;
- volatile uint32_t APB2RSTR;
- volatile uint32_t APB1RSTR;
- volatile uint32_t AHBENR;
- volatile uint32_t APB2ENR;
- volatile uint32_t APB1ENR;
- volatile uint32_t BDCR;
- volatile uint32_t CSR;
- #elif defined(STM32F4)
- volatile uint32_t CR;
- volatile uint32_t PLLCFGR;
- volatile uint32_t CFGR;
- volatile uint32_t CIR;
- volatile uint32_t AHB1RSTR;
- volatile uint32_t AHB2RSTR;
- volatile uint32_t AHB3RSTR;
- volatile uint32_t AHB4RSTR; // Reserved
- volatile uint32_t APB1RSTR;
- volatile uint32_t APB2RSTR;
- volatile uint32_t APB3RSTR; // Reserved
- volatile uint32_t APB4RSTR; // Reserved
- volatile uint32_t AHB1ENR;
- volatile uint32_t AHB2ENR;
- volatile uint32_t AHB3ENR;
- volatile uint32_t AHB4ENR; // Reserved
- volatile uint32_t APB1ENR;
- volatile uint32_t APB2ENR;
- volatile uint32_t APB3ENR; // Reserved
- volatile uint32_t APB4ENR; // Reserved
- volatile uint32_t AHB1LPENR;
- volatile uint32_t AHB2LPENR;
- volatile uint32_t AHB3LPENR;
- volatile uint32_t AHB4LPENR; // Reserved
- volatile uint32_t APB1LPENR;
- volatile uint32_t APB2LPENR;
- volatile uint32_t APB3LPENR; // Reserved
- volatile uint32_t APB4LPENR; // Reserved
- volatile uint32_t BDCR;
- volatile uint32_t CSR;
- volatile uint32_t _1;
- volatile uint32_t _2;
- volatile uint32_t SSCGR;
- volatile uint32_t PLLI2SCFGR;
- #endif
-
- #if defined(STM32F1)
- enum AHB_dev {
- DMA1 = 1 << 0,
- DMA2 = 1 << 1,
- SRAM = 1 << 2,
- FLITF = 1 << 4,
- CRC = 1 << 6,
- FSMC = 1 << 8,
- SDIO = 1 << 10
- };
-
- enum APB1_dev {
- TIM2 = 1 << 0,
- TIM3 = 1 << 1,
- TIM4 = 1 << 2,
- TIM5 = 1 << 3,
- TIM6 = 1 << 4,
- TIM7 = 1 << 5,
- TIM12 = 1 << 6,
- TIM13 = 1 << 7,
- TIM14 = 1 << 8,
- WWDG = 1 << 11,
- SPI2 = 1 << 14,
- SPI3 = 1 << 15,
- USART2 = 1 << 17,
- USART3 = 1 << 18,
- UART4 = 1 << 19,
- UART5 = 1 << 20,
- I2C1 = 1 << 21,
- I2C2 = 1 << 22,
- USB = 1 << 23,
- CAN = 1 << 25,
- BKP = 1 << 27,
- PWR = 1 << 28,
- DAC = 1 << 29
- };
-
- enum APB2_dev {
- AFIO = 1 << 0,
- IOPA = 1 << 2,
- IOPB = 1 << 3,
- IOPC = 1 << 4,
- IOPD = 1 << 5,
- IOPE = 1 << 6,
- IOPF = 1 << 7,
- IOPG = 1 << 8,
- ADC1 = 1 << 9,
- ADC2 = 1 << 10,
- TIM1 = 1 << 11,
- SPI1 = 1 << 12,
- TIM8 = 1 << 13,
- USART1 = 1 << 14,
- ADC3 = 1 << 15,
- TIM9 = 1 << 19,
- TIM10 = 1 << 20,
- TIM11 = 1 << 21
- };
- #elif defined(STM32F4)
- enum AHB1_dev {
- GPIOA = 1 << 0,
- GPIOB = 1 << 1,
- GPIOC = 1 << 2,
- GPIOD = 1 << 3,
- GPIOE = 1 << 4,
- GPIOF = 1 << 5,
- GPIOG = 1 << 6,
- GPIOH = 1 << 7,
- GPIOI = 1 << 8,
- CRC = 1 << 12,
- DMA1 = 1 << 21,
- DMA2 = 1 << 22,
- ETHMAC = 1 << 25,
- OTGHS = 1 << 29,
- };
-
- enum AHB2_dev {
- DCMI = 1 << 0,
- CRYP = 1 << 4,
- HASH = 1 << 5,
- RNG = 1 << 6,
- OTGFS = 1 << 7,
- };
-
- enum AHB3_dev {
- FSMC = 1 << 0,
- };
-
- enum APB1_dev {
- TIM2 = 1 << 0,
- TIM3 = 1 << 1,
- TIM4 = 1 << 2,
- TIM5 = 1 << 3,
- TIM6 = 1 << 4,
- TIM7 = 1 << 5,
- TIM12 = 1 << 6,
- TIM13 = 1 << 7,
- TIM14 = 1 << 8,
- WWDG = 1 << 11,
- SPI2 = 1 << 14,
- SPI3 = 1 << 15,
- USART2 = 1 << 17,
- USART3 = 1 << 18,
- UART4 = 1 << 19,
- UART5 = 1 << 20,
- I2C1 = 1 << 21,
- I2C2 = 1 << 22,
- I2C3 = 1 << 23,
- CAN1 = 1 << 25,
- CAN2 = 1 << 26,
- PWR = 1 << 28,
- DAC = 1 << 29,
- };
-
- enum APB2_dev {
- TIM1 = 1 << 0,
- TIM8 = 1 << 1,
- USART1 = 1 << 4,
- USART6 = 1 << 5,
- ADC = 1 << 8,
- SDIO = 1 << 11,
- SPI1 = 1 << 12,
- SYSCFG = 1 << 14,
- TIM9 = 1 << 16,
- TIM10 = 1 << 17,
- TIM11 = 1 << 18,
- };
- #endif
-
- #if defined(STM32F1)
- inline void enable(AHB_dev dev) {
- AHBENR |= dev;
- }
- #elif defined(STM32F4)
- inline void enable(AHB1_dev dev) {
- AHB1ENR |= dev;
- }
-
- inline void enable(AHB2_dev dev) {
- AHB2ENR |= dev;
- }
-
- inline void enable(AHB3_dev dev) {
- AHB3ENR |= dev;
- }
- #endif
- inline void enable(APB1_dev dev) {
- APB1ENR |= dev;
- }
-
- inline void enable(APB2_dev dev) {
- APB2ENR |= dev;
- }
-};
-
-#if defined(STM32F1)
-static RCC_t& RCC = *(RCC_t*)0x40021000;
-#elif defined(STM32F4)
-static RCC_t& RCC = *(RCC_t*)0x40023800;
-#endif
-
struct STK_t {
volatile uint32_t CTRL;
volatile uint32_t LOAD;
@@ -251,28 +42,6 @@ struct STK_t {
static STK_t& STK = *(STK_t*)0xe000e010;
-struct FLASH_t {
- volatile uint32_t ACR;
- volatile uint32_t KEYR;
- volatile uint32_t OPTKEYR;
- volatile uint32_t SR;
- volatile uint32_t CR;
- #if defined(STM32F1)
- volatile uint32_t AR;
- volatile uint32_t RESERVED;
- volatile uint32_t OBR;
- volatile uint32_t WRPR;
- #elif defined(STM32F4)
- volatile uint32_t OPTCR;
- #endif
-};
-
-#if defined(STM32F1)
-static FLASH_t& FLASH = *(FLASH_t*)0x40022000;
-#elif defined(STM32F4)
-static FLASH_t& FLASH = *(FLASH_t*)0x40023c00;
-#endif
-
struct I2C_t {
volatile uint32_t CR1;
volatile uint32_t CR2;
diff --git a/hal/usart.h b/hal/usart.h
index 484d89e..78a28dc 100644
--- a/hal/usart.h
+++ b/hal/usart.h
@@ -1,6 +1,7 @@
#ifndef USART_H
#define USART_H
+#include "rcc.h"
#include "stm32.h"
#include "interrupt.h"
#include "thread.h"